Basic VLSI - Very Large Scale Integration MCQ
1. Why is FET used as a buffer amplifier?
Answer
Correct Answer:
Because it has high input impedance and low output impedance
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2. In which region should MOS be operated as an amplifier?
Answer
Correct Answer:
It should be operated in the Saturation region
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3. The gain of the CG configuration is __________ the CS configuration.
Answer
Correct Answer:
more than
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4. Which IEEE standard is used by VHDL 93 ?
Answer
Correct Answer:
IEEE 1164
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5. Why is the fabrication of inductors in ICs not practical?
Answer
Correct Answer:
The depth dimensions are very small as compared to the lateral dimensions
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6. We need only __________ to make a 2:1 MUX with a pass transistor logic.
Answer
Correct Answer:
7 transistors
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7. Which of the following statements does not perform any action?
Answer
Correct Answer:
The Null statement
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8. The CMRR (common-mode rejection ratio) of a differential amplifier must be ____.
Answer
Correct Answer:
as high as possible
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9. Wafers with a____________ are needed for the fabrication of VLSI.
Answer
Correct Answer:
large diameter
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10. In VHDL,the order of the concurrent statements must be_________.
Answer
Correct Answer:
both increasing and decreasing
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11. Which one of the following is true about the fabrication of capacitors in the ICs?
Answer
Correct Answer:
For large capacitance, a larger area is required
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12. Which one of the following stages is used in the Cascode configuration?
Answer
Correct Answer:
CS and CG Stage
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13. What does Fick's law deal with?
Answer
Correct Answer:
The diffusion rate of impurities in a semi-conductor
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14. The most commonly used model for scaling is ___________ .
Answer
Correct Answer:
Both of these
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15. When do Sequential statements appear in a program?
Answer
Correct Answer:
They appear only inside of a process block and subprogram
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16. Which one of the following has the lowest power dissipation?
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17. Which one of the following is not true about packages in VHDL?
Answer
Correct Answer:
A package cannot be shared by several designs
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18. Which diode is present in the GaAs MESFET circuit?
Answer
Correct Answer:
A Schottky diode at the gate region of GaAs MESFETs
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19. In comparison with SSI ,VLSI has ____________ components per chip.
Answer
Correct Answer:
105 or more
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20. Which one of the following is not a CMOS fabrication technique?
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21. MOS in the Common Gate Configuration provides___________.
Answer
Correct Answer:
Non inverted gain
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22. Which kind of signal is converted into in the common source arrangement of the transistor?
Answer
Correct Answer:
Current signal
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23. In which condition is the Case statement used?
Answer
Correct Answer:
When the behavior of design depends on the value of one signal expression
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24. The two metal layers are laid in a way that ______________.
Answer
Correct Answer:
the conductors are always orthogonal
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25. Which of the following parameters is advantageous in the case of BiCMOS technology?
Answer
Correct Answer:
High o/p drive current
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26. Which of the following can act as a dopant for the formation of N-type gallium arsenide material?
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27. What is the body effect on the input impedance of the Common Gate Configuration?
Answer
Correct Answer:
It decreases the input impedance
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28. In VHDL, the prefix "V" stands for _____ .
Answer
Correct Answer:
VHSIC (very high speed integrated circuit)
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29. In the Cascode structure, the maximum voltage gain is roughly equal to ____________.
Answer
Correct Answer:
the square of the intrinsic gain of the transistors
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30. Which kind of problem is eliminated by the NMOS superbuffers?
Answer
Correct Answer:
Asymmetry of the conventional inverter
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31. Stick diagrams are used to __________.
Answer
Correct Answer:
convey the layer information
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32. If length (L) and width (W) are both scaled down by α, the area is scaled ___________. ron
Answer
Correct Answer:
None of these
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33. Which among the following conditions qualifies for a Latch-up in CMOS circuit condition?
Answer
Correct Answer:
When a low resistance path is established between the drain and the source
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34. Under what condition does the Frenkel defect take place?
Answer
Correct Answer:
A silicon atom in an interstitial lattice site with an associated vacancy
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35. QHDL(Hardware Description Language) is used for _____________.
Answer
Correct Answer:
hardware design of circuits
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36. In the BiCMOS process, the basic inverter is made by __________.
Answer
Correct Answer:
using mos as switch and BJT as driver
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37. Photolithography in IC Fabrication is___________.
Answer
Correct Answer:
the selective removal of oxide in the desired areas
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38. Which one of the following is a concurrent statement?
Answer
Correct Answer:
The process statement
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39. LSI and VLSI devices use_____________ technology.
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40. Which one of the following is not a sequential statement in VHDL?
Answer
Correct Answer:
The Block statement
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41. When is the Boundary Scan Test (BST) used?
Answer
Correct Answer:
It is used to resolve problems associated with the testing of boards carrying VLSI circuits
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42. Which of the following is the fastest technology in terms of propagation delay?
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43. What is the function of the Alias statement?
Answer
Correct Answer:
It declares an alternate name for an existing named entity
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44. What function does the scalar data type perform in VHDL?
Answer
Correct Answer:
It does not provide element values
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45. What does the Programmable Logic Array(PLA) consist of?
Answer
Correct Answer:
A programmable AND array and a programmable OR array
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46. In the Folded Cascode structure, ____________.
Answer
Correct Answer:
both of the above
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47. If length (L) and width (W) are both scaled down by α, the area is scaled down by __________.
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48. Which one of the following is not a mode for ports in VHDL?
Answer
Correct Answer:
Tri-state
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49. Which one of the following statements is not correct about an entity in VHDL?
Answer
Correct Answer:
One entity has only one architecture
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50. The Cascode structure ___________.
Answer
Correct Answer:
has high output impedance
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51. Which execution platform is used for a behaviour-level VHDL?
Answer
Correct Answer:
Operating system
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52. MOS current sources are used to generate __________.
Answer
Correct Answer:
All of these
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53. In general, VDD and VSS are always distributed upon ____________.
Answer
Correct Answer:
Metal Layers
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54. The Double Metal MOS process is used to ____________.
Answer
Correct Answer:
None of the above
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55. What is Generic Array Logic(GAL) based on?
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56. Latch up introduces_________.
Answer
Correct Answer:
a low resistance path between the power supply and the ground
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57. What exactly is Behavioral Modeling in VHDL?
Answer
Correct Answer:
A set of sequential program statements
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58. If length (L) and width (W) are both scaled down by α, the area is scaled ___________. (Power Speed Product PT)
Answer
Correct Answer:
down by α2
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59. The separation between the Thinox Regions is of __________ .
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60. What is Metallization in IC Fabrication?
Answer
Correct Answer:
It is a process by which the components of an IC are inter connected by an aluminum conductor
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61. For the Orbit Process, the n-active and p-active regions have_________.
Answer
Correct Answer:
negligible capacitance
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62. High Electron Mobility Transistors(HEMT) are formed using alternating layers of _______________.
Answer
Correct Answer:
GaAs and AlGaAs
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63. A fast CMOS circuit requires that the gm___________. (Where gm means transconductance).
Answer
Correct Answer:
should be high
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64. For a given total bias current, the gain of a differential pair is________ more than the CS Stage.
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65. A signal data object in VHDL is an object with_______________.
Answer
Correct Answer:
a past history of values
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66. Contacts between the metal layers are known as _____________.
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67. For an npn Bipolar Transistor, gm ___________.
Answer
Correct Answer:
All of these
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68. Floating point data types provide an approximation of ___________.
Answer
Correct Answer:
even numbers
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69. An active current mirror means that ___________.
Answer
Correct Answer:
active devices are used as load
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VLSI - Very Large Scale Integration MCQs | Topic-wise
