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Microprocessor and Microcontrollers MCQ

1. ________ is usually the first level of memory access by the microprocessor

Cache memory

Data memory

Main memory

All of these

Answer

Correct Answer: Cache memory

Note: This Question is unanswered, help us to find answer for this one

2. The offset of a particular segment varies from _________

000H to FFFH

0000H to FFFFH

00H to FFH

00000H to FFFFFH

Answer

Correct Answer: 0000H to FFFFH

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3. AL stand for

Accumulator low

Address low

Appropriate low

Application low

Answer

Correct Answer: Accumulator low

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4. AH stand for

Accumulator high

Address high

Appropriate high

Application high

Answer

Correct Answer: Accumulator high

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5. PC stand for

Program counter

Project counter

Protect counter

Planning counter

Answer

Correct Answer: Program counter

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6. NMI stand for

Non mask able interrupt

Non mistake interrupt

Both

None of these

Answer

Correct Answer: Non mask able interrupt

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7. AD stand for

Address data

Address delete

Address date

Address deal

Answer

Correct Answer: Address data

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8. ALE stand for

Address latch enable

Address light enable

Address lower enable

Address last enable

Answer

Correct Answer: Address latch enable

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9. SI stand for

Stand index

Source index

Segment index

Simple index

Answer

Correct Answer: Source index

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10. DI stand for

Destination index

Defect index

Definition index

Delete index

Answer

Correct Answer: Destination index

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11. BP stand for

Bit pointer

Base pointer

Bus pointer

Byte pointer

Answer

Correct Answer: Base pointer

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12. EA stand for

Effective address

Electrical address

Effect address

None of these

Answer

Correct Answer: Effective address

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13. SBA stand for

Segment bus address

Segment bit address

Segment base address

Segment byte address

Answer

Correct Answer: Segment base address

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14. PA stand for

Project address

Physical address

Pin address

Pointer address

Answer

Correct Answer: Physical address

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15. DIP stand for

Deal inline package

Dual inline package

Direct inline package

Digital inline package

Answer

Correct Answer: Dual inline package

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16. The pin configuration of 8086 is available in the________

40 pin

50 pin

30 pin

20 pin

Answer

Correct Answer: 40 pin

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17. The _______ address of a memory is a 20 bit address for the 8086 microprocessor

Physical

Logical

Both

None of these

Answer

Correct Answer: Physical

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18. The physical address of memory is

20 bit

16 bit

32 bit

64 bit

Answer

Correct Answer: 20 bit

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19. The size of each segment in 8086 is

64 kb

24 kb

50 kb

16kb

Answer

Correct Answer: 64 kb

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20. How many type of addressing in memory

Logical address

Physical address

Both A and B

None of these

Answer

Correct Answer: Both A and B

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21. How many bits the instruction pointer is wide

16 bit

32 bit

64 bit

128 bit

Answer

Correct Answer: 16 bit

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22. Which register containing the 8086/8088 flag

Status register

Stack register

Flag register

Stand register

Answer

Correct Answer: Status register

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23. Which has great important in modular programming

Stack segment

Queue segment

Array segment

All of these

Answer

Correct Answer: Stack segment

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24. The lower 8 bit are called_______

Answer

Correct Answer: AL

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25. The acculatator is 16 bit wide and is called

Answer

Correct Answer: AX

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26. Which are the segment

CS: Code segment

DS: data segment

SS: Stack segment

ES:extra segment

All of these

Answer

Correct Answer: All of these

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27. DS Stand for

Data segment

Direct segment

Declare segment

Divide segment

Answer

Correct Answer: Data segment

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28. CS Stand for

Code segment

Coot segment

Cost segment

Counter segment

Answer

Correct Answer: Code segment

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29. IP Stand for

Instruction pointer

Instruction purpose

Instruction paints

None of these

Answer

Correct Answer: Instruction pointer

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30. Which are the four categories of registers:

General‐ purpose register

Pointer or index registers

Segment registers

Other register

All of these

Answer

Correct Answer: All of these

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31. Which are the part of architecture of 8086

The bus interface unit

The execution unit

Both A and B

None of these

Answer

Correct Answer: Both A and B

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32. EU STAND FOR

Execution unit

Execute unit

Exchange unit

None of these

Answer

Correct Answer: Execution unit

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33. BIU STAND FOR:

Bus interface unit

Bess interface unit

A and B

None of these

Answer

Correct Answer: Bus interface unit

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34. When .9432 E – 4 is subtracted from .5452 E – 3 in normalized floating point mode

none of the numbers is changed

9432 E – 4 is changed to .09432 E – 3 and .5452 E – 3 is not changed

5452 E – 3 is changed to 5.452 E – 4 but .9432 E – 4 is not changed

both Ihe numbers are changed and their exponents are, made equal to -5

Answer

Correct Answer: 9432 E – 4 is changed to .09432 E – 3 and .5452 E – 3 is not changed

Note: This Question is unanswered, help us to find answer for this one

35. MS Access is a DBMS software.

True

False

Answer

Correct Answer: True

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36. An I/O processor controls the flow of information between

cache memory and I/O devices

main memory and I/O devices

two I/O devices

cache and main memory

Answer

Correct Answer: main memory and I/O devices

Note: This Question is unanswered, help us to find answer for this one

37. IC 7485 cannot be cascadeD.

True

False

Answer

Correct Answer: False

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38. Which of the following is not treated as hexadecimal constant by assembler in 8085?

45 H

6 AFH

234

64 H

Answer

Correct Answer: 234

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39. Assertion (A): Negative values of incremental operator in DO loop are allowed in Fortran 77 but not in earlier versions of Fortran.

Both A and R are correct and R is correct explanation of A

Both A and R are correct but R is not correct explanation of A

A is correct R is wrong

A is wrong R is correct

Answer

Correct Answer: Both A and R are correct but R is not correct explanation of A

Note: This Question is unanswered, help us to find answer for this one

40. A real number consists of

integer part

integer part and fraction part

integer part, fraction part along with positive or negative sign

none of the above

Answer

Correct Answer: integer part, fraction part along with positive or negative sign

Note: This Question is unanswered, help us to find answer for this one

41. The number of interrupt lines in 8085 is

Answer

Correct Answer: 5

Note: This Question is unanswered, help us to find answer for this one

42. ‘Burst refresh’ in DRAM is also called

Concentrated refresh

Distributed refresh

Hidden refresh

None of the above

Answer

Correct Answer: Concentrated refresh

Note: This Question is unanswered, help us to find answer for this one

43. Which of the following pair of gates can form a latch?

a pair of cross coupled OR

a pair of cross copled AND

a pair of cross coupled NAND

a cross coupled NAND/OR

Answer

Correct Answer: a pair of cross coupled NAND

Note: This Question is unanswered, help us to find answer for this one

44. Which of the following conditions is not allowed in an RS latch?

R is asserted, S is asserted

R is asserted, S is negated

R is negated, S is asserted

R is negated, S is negated

Answer

Correct Answer: R is asserted, S is asserted

Note: This Question is unanswered, help us to find answer for this one

45. For the number A[15:0] = 0110110010001111, A[14:13] is ______ A[3:2].

less than

greater than

the same as

cannot be determined

Answer

Correct Answer: the same as

Note: This Question is unanswered, help us to find answer for this one

46. If m is a power of 2, the number of select lines required for an m-input mux is:

2^m

log2 (m)

2*m

Answer

Correct Answer: log2 (m)

Note: This Question is unanswered, help us to find answer for this one

47. If the number of address bits in a memory is reduced by 2 and the address ability is doubled, the size of the memory (i.e., the number of bits stored in the memory)

doubles

remains unchanged

halves

increases by 2^(address bits)/addressability

Answer

Correct Answer: halves

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48. Of the following circuits, the one which involves storage is

RS Latch

mux

nand

decoder

Answer

Correct Answer: RS Latch

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49. We say that a set of gates is logically complete if we can build any circuit without using any other kind of gates. Which of the following sets are logically complete

set of {AND,OR}

set of {EXOR, NOT}

set of {AND,OR,NOT}

None of the above

Answer

Correct Answer: set of {AND,OR,NOT}

Note: This Question is unanswered, help us to find answer for this one

50. A structure that stores a number of bits taken “together as a unit” is a

gate

mux

decoder

Answer

Correct Answer: register

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51. When the write enable input is not asserted, the gated D latch ______ its output.

can not change

clears

sets

complements

Answer

Correct Answer: can not change

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52. Circuit A is a 1-bit adder; circuit B is a 1 bit multiplier.

Circuit A has more gates than circuit B

Circuit B has more gates than circuit A

Circuit A has the same number of gates as circuit B (Hint: Construct the truth table for the adder and the multiplier)

Answer

Correct Answer: Circuit A has more gates than circuit B

Note: This Question is unanswered, help us to find answer for this one

53. Because we wish to allow each ASCII code to occupy one location in memory, most memories are _____ addressable.

BYTE

NIBBLE

WORD (16 bits)

DOUBLEWORD (32 bits)

Answer

Correct Answer: BYTE

Note: This Question is unanswered, help us to find answer for this one

54. For a memory with a 16-bit address space, the address ability is

16 bits

8 bits

2^16 bits

Cannot be determined

Answer

Correct Answer: Cannot be determined

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55. Using DeMorgan’s Theorem we can convert any AND-OR structure into

NAND-NAND

OR-NAND

NAND-NOR

NOR-NAND

Answer

Correct Answer: NAND-NAND

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56. The minimum number of transistors required to implement a two input AND gate is

Answer

Correct Answer: 6

Note: This Question is unanswered, help us to find answer for this one

57. Which pins are general purpose I/O pins during mode-2 operation of the 82C55?

PA0 – PA7

PB0-PB7

PC3-PC7

PC0-PC2

Answer

Correct Answer: PA0 – PA7

Note: This Question is unanswered, help us to find answer for this one

58. SDRAM refers to

Static DRAM

Synchronous DRAM

Sequential DRAM

Semi DRAM

Answer

Correct Answer: Synchronous DRAM

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59. What do the symbols [ ] indicate?

Direct addressing

Indirect addressing

None of the above

Answer

Correct Answer: Indirect addressing

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60. Conversion of the +1000 decimal number into signed binary word results

0000 0011 1110 1000

1111 1100 0001 1000

1000 0011 1110 1000

0111 1100 0001 1000

Answer

Correct Answer: 1000 0011 1110 1000

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61. In 80186, the timer which connects to the system clock is

Timer 0

Timer 1

Timer 2

Any one can be connected

Answer

Correct Answer: Timer 2

Note: This Question is unanswered, help us to find answer for this one

62. Data rate available for use on USB is

12 Mbits per second

1.5 Mbits per second

Both (A) and (B)

No restriction

Answer

Correct Answer: Both (A) and (B)

Note: This Question is unanswered, help us to find answer for this one

63. NMI input is

Edge sensitive

Level sensitive

Both edge and level triggered

Edge triggered and level sensitive

Answer

Correct Answer: Edge triggered and level sensitive

Note: This Question is unanswered, help us to find answer for this one

64. The no. of wait states required to interface 8279 to 8086 with 8MHz clock are

Two

Three

One

None

Answer

Correct Answer: Two

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65. The no. of address lines required to address a memory of size 32 K is

15 lines

16 lines

18 lines

14 lines

Answer

Correct Answer: 15 lines

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66. The time required to refresh a typical DRAM is

2 – 4 us

2 – 4 ns

2 – 4 ms

2 – 4 ps

Answer

Correct Answer: 2 – 4 ms

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67. A Bus cycle is equal to how many clocking periods

Two

Three

Four

Six

Answer

Correct Answer: Four

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68. The flash memory is programmed in the system by 12 V programming pulse

TRUE

FALSE

Answer

Correct Answer: TRUE

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69. If the programmable counter timer 8254 is set in mode 1 and is to be used to count six events, the output will remain at logic 0 for _____ number of counts

All of the above

Answer

Correct Answer: 6

Note: This Question is unanswered, help us to find answer for this one

70. The first task of DOS operating system after loading into the memory is to use the file called___________

HIMEM.SYS

CONFIG.SYS

AUTOEXEC.BAT

SYSTEM.INI

Answer

Correct Answer: CONFIG.SYS

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71. Software command CLEAR MASK REGISTER in DMA

Disables all channels.

Enables all channels.

None

Clears first/last flip-flop within 8237.

Answer

Correct Answer: Enables all channels.

Note: This Question is unanswered, help us to find answer for this one

72. The first modern computer was called_____________

FLOW-MATIC

UNIVAC-I

ENIAC

INTEL

Answer

Correct Answer: ENIAC

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73. The VESA local bus operates at

8 MHz

33 MHz

16 MHz

None of these

Answer

Correct Answer: 33 MHz

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74. Which of the following statement is false?

RTOS performs tasks in predictable amount of time

Windows 98 is RTOS

Interrupts are used to develop RTOS

Kernel is the one of component of any OS

Answer

Correct Answer: Windows 98 is RTOS

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75. Which microprocessor pins are used to request and acknowledge a DMA transfer?

Reset and ready

Ready and wait

HOLD and HLDA

None o these

Answer

Correct Answer: HOLD and HLDA

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76. When the 82C55 is reset, its I/O ports are all initializes as

Output port using mode 0

Input port using mode 1

Output port using mode 1

Input port using mode 0

Answer

Correct Answer: Input port using mode 0

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77. The memory data bus width in Pentium is

16 bit

32 bit

64 bit

None of these

Answer

Correct Answer: 64 bit

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78. By what factor does the 8284A clock generator divide the crystal oscillator’s output frequency?

One

Two

Three

Four

Answer

Correct Answer: Three

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79. 8088 microprocessor has

16 bit data bus

4 byte pre-fetch queue

6 byte pre-fetch queue

16 bit address bus

Answer

Correct Answer: 16 bit address bus

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80. 8251 is a

UART

USART

Programmable Interrupt controller

Programmable interval timer/counter

Answer

Correct Answer: USART

Note: This Question is unanswered, help us to find answer for this one

81. Which of the following statement is true?

The group of machine cycle is called a state.

A machine cycle consists of one or more instruction cycle.

An instruction cycle is made up of machine cycles and a machine cycle is made up of number of states.

None of the above

Answer

Correct Answer: A machine cycle consists of one or more instruction cycle.

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82. The PCI bus is the important bus found in all the new Pentium systems because

It has plug and play characteristics

It has ability to function with a 64 bit data bus

Any Microprocessor can be interfaced to it with PCI controller or bridge

All of the above

Answer

Correct Answer: All of the above

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83. Signal voltage ranges for a logic high and for a logic low in RS-232C standard are

Low = 0 volt to 1.8 volt, high = 2.0 volt to 5 volt

Low =-15 volt to –3 vol, high = +3 volt to +15 volt

Low = +3 volt to +15 volt, high = -3 volt to -15 volt

Low = 2 volt to 5.0 volt, high = 0 volt to 1.8 volt

Answer

Correct Answer: Low =-15 volt to –3 vol, high = +3 volt to +15 volt

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84. EPROM is generally erased by using

Ultraviolet rays

Infrared rays

12 V electrical pulse

24 V electrical pulse

Answer

Correct Answer: Ultraviolet rays

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85. The Pentium microprocessor has______execution units.

Answer

Correct Answer: 3

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86. LOCK prefix is used most often

During normal execution.

During DMA accesses

During interrupt servicing

During memory accesses

Answer

Correct Answer: During interrupt servicing

Note: This Question is unanswered, help us to find answer for this one

87. Itanium processor of Intel is a

32 bit microprocessor.

64 bit microprocessor.

128 bit microprocessor.

256 bit microprocessor

Answer

Correct Answer: 64 bit microprocessor.

Note: This Question is unanswered, help us to find answer for this one

88. In case of DVD, the speed is referred in terms of n X (for example 32 X). Here, X refers to

150 KB/s

300 KB/s

1.38 MB/s

2.4 MB/s

Answer

Correct Answer: 1.38 MB/s

Note: This Question is unanswered, help us to find answer for this one

89. SD RAM refers to

Synchronous DRAM

Static DRAM

Semi DRAM

Second DRAM

Answer

Correct Answer: Synchronous DRAM

Note: This Question is unanswered, help us to find answer for this one

90. In the instruction FADD, F stands for

Far

Floppy

Floating

File

Answer

Correct Answer: Floating

Note: This Question is unanswered, help us to find answer for this one

91. These are two ways in which a microprocessor can come out of Halt state.

When hold line is a logical 1

When interrupt occurs and the interrupt system has been enabled

When both (A) and (B) are true

When either (A) or (B) are true

Answer

Correct Answer: When hold line is a logical 1

Note: This Question is unanswered, help us to find answer for this one

92. String instructions.

2. Ready pin of a microprocessor is used

To indicate that the microprocessor is ready to receive inputs

To indicate that the microprocessor is ready to receive outputs

To introduce wait states

To provide direct memory access

Answer

Correct Answer: To introduce wait states

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93. Direction flag is used with

String instructions.

Stack instructions

Arithmetic instructions

Branch instructions

Answer

Correct Answer: String instructions.

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94. What will be the contents of register AL after the following has been executed MOV BL, 8C MOV AL, 7E ADD AL, BL

0A and carry flag is set

0A and carry flag is reset

6A and carry flag is set

6A and carry flag is reset

Answer

Correct Answer: 0A and carry flag is set

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95. Number of the times the instruction sequence below will loop before coming out of loop is MOV AL, 00h A1: INC AL JNZ A1

255

256

Answer

Correct Answer: 256

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96. Pseudo instructions are basically

False instructions.

Instructions that are ignored by the microprocessor

Assembler directives

Instructions that are treated like comments

Answer

Correct Answer: Assembler directives

Note: This Question is unanswered, help us to find answer for this one

97. Which of the following is true with respect to EEPROM?

Contents can be erased byte wise only.

Contents of full memory can be erased together

Contents can be erased using ultra violet rays

Contents can not be erased

Answer

Correct Answer: Contents can be erased using ultra violet rays

Note: This Question is unanswered, help us to find answer for this one

98. A certain SRAM has CS = 0 , WE = 0 and OE = 1. In which of the following modes this SRAM is operating

Read

Write

Stand by

None of the above

Answer

Correct Answer: Write

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99. Which type of JMP instruction assembles if the distance is 0020 h bytes

Near.

Far

Short

None of the above.

Answer

Correct Answer: Near.

Note: This Question is unanswered, help us to find answer for this one

100. In a DMA write operation the data is transferred

From I/O to memory.

From memory to I/O.

From memory to memory.

From I/O to I/O.

Answer

Correct Answer: From I/O to memory.

Note: This Question is unanswered, help us to find answer for this one

101. If a 1M ×1 DRAM requires 4 ms for a refresh and has 256 rows to be refreshed, no more than __________ of time must pass before another row is refreshed.

64 ms.

4 ns.

0.5 ns.

15.625 µs

Answer

Correct Answer: 4 ns.

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102. In which T-state does the CPU sends the address to memory or I/O and the ALE signal for demultiplexing

T1.

T2.

T3.

T4.

Answer

Correct Answer: T1.

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103. If the crystal oscillator is operating at 15 MHz, the PCLK output of 8284 is

2.5 MHz.

5 MHz.

7.5 MHz.

10 MHz.

Answer

Correct Answer: 2.5 MHz.

Note: This Question is unanswered, help us to find answer for this one

104. Which memory is used to holds the address of the data stored in the cache

Associative memory

Case memory

Ordinary memory

None of these

Answer

Correct Answer: Associative memory

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105. Which is the type of cache memory

Fully associative cache

Direct‐mapped cache

Set‐associative cache

All of these

Answer

Correct Answer: All of these

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