The SCE-MI provides a transport infrastructure between the _____ and the host workstation sides of each channel which interconnects transactor models in the emulator to C (untimed or RTL) models on the workstation?

To record the trace information generated by the Cortex-M3/M4 processors, Lauterbach supports following modes? (check all that apply)

Choose the most probable reason for the compile error. If you are developing code for an early model ARM Cortex processor, your code fails to build and when you remove the line below the code compiles successfully? t = t + 0.01

The complete data exchange between the simulation and the μC is realized via the standard debugger interface, so the hardware effort for the coupling is minimal in comparison to other HIL simulation approaches where every ____ pin itself has to be connected to the interface of the simulation computer?

On reset, What happens in an embedded system?

Using a TRACE32, the generated code was loaded into the control hardware and functionally tested in-situ?

What number should be loaded into the TH register using mode 2 to get 100μsec delay? (Assume XTAL=11.0592MHz)

The Atmega 16 micro controller is a __________.

How many times is the following loop performed? MOV R6, #200 BACK: MOV R5, #100 HERE: DJNZ R5, HERE DJNZ R6, BACK

Which devices are used in Embedded Systems?

Which one of the following files is produced by an 8051 assembler?